Εμφάνιση απλής εγγραφής

dc.contributor.authorBrokalakis, A.
dc.contributor.authorKakarountas, Athanasios P.
dc.contributor.authorGoutis, Costas E.
dc.date.accessioned2015-07-25T09:31:12Z
dc.date.available2015-07-25T09:31:12Z
dc.date.issued2005-11-02
dc.identifier.isbn0-7803-9333-3
dc.identifier.issn1520-6130
dc.identifier.otherDOI: 10.1109/SIPS.2005.1579849
dc.identifier.urihttp://hdl.handle.net/123456789/1000
dc.description.abstractAdvanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter cryptographic primitive is proposed. It presents the highest performance (in terms of throughput) among competitive academic and commercial implementations. Using a Virtex-II device, a 1.94 Gbps throughput is achieved, while the memory usage remains low (8 BlockRAMs) and the CLB coverage moderate.el
dc.language.isoenel
dc.publisherIEEEel
dc.relation.ispartofseriesSignal Processing Systems Design and Implementation, 2005. IEEE Workshop on;pp.116-121
dc.subjectcryptographyel
dc.subjectfield programmable gate arraysel
dc.subjectAES-128 encryptionel
dc.subjectAdvanced Encryption Standardel
dc.subjectFPGA implementationel
dc.subjectVirtex-II deviceel
dc.subjectcryptographic primitiveel
dc.titleA high-throughput area efficient FPGA implementation of AES-128 Encryptionel
dc.typeArticleel


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Εμφάνιση απλής εγγραφής